(1) Field of the Invention
The present invention relates to a sense amplifier circuit and, more particularly, to a current sense amplifier circuit for use in a semiconductor memory device.
(2) Description of the Related Art
A current sense amplifier circuit is usually used as a read or retrieve circuit, which is connected to a semiconductor memory section provided in a semiconductor memory device. More specifically, the current sense amplifier circuit judges whether there flows or not a very small current based on the storage information read out from the semiconductor memory section, and provides the result of such judgment as an output correspondence to an electric level of "1" or "0".
FIG. 1 is a circuit diagram showing a prior art current sense amplifier circuit, FIG. 2 is a waveform chart illustrating the operation of the prior art circuit in the case where a current flows when the semiconductor memory section is accessed, and FIG. 3 is a waveform chart illustrating the operation of the same prior art circuit in the case where no currents flow when the semiconductor memory section is accessed.
The current sense amplifier circuit, as shown in FIG. 1, is a subordinate circuit connected to a semiconductor memory section which includes an N-channel selecting transistor 5 (hereinafter referred to as a "Y-selector"), N-channel access transistors 6, 7, and a parasitic capacitor 9. The line connecting the source of the Y-selector 5 with the respective drains of the access transistors 6, 7 and including a node C to which the parasitic capacitor 9 is coupled is hereinafter referred to as a "digit line or column line C".
The current sense amplifier circuit forms a current mirror circuit. More specifically, the current sense amplifier circuit comprises P-channel transistors 1 and 2; a complimentary inverter 8; an N-channel transistor 3 receiving as a gate input the output signal of the complementary inverter 8 and having a source connected to the input terminal of the complementary inverter 8 and also to the drain side B of the Y-selector 5 and a drain connected to the drain side A of the P-channel transistor 1; and an N-channel transistor 4 constituting with the P-channel transistor 2 a ratio inverter.
Next, the operation of the circuit will be explained with reference to the graph shown in FIG. 2.
When a high level input is inputted on input terminals (row lines) A1 and A3 at an instant t1 as shown in FIG. 2. the N-channel transistor 7 in the semiconductor memory section is selected. Thus, the N-channel transistor 7 and the Y-selector 5 both are turned on.
As shown in FIG. 2, the potential levels at the respective nodes are as follows. The potential at the node B momentarily becomes lower than the inversion level (threshold level) of the complementary inverter 8 in charging a parasitic capacitor 9 coupled to the digit line C. After the completion of charging of the parasitic capacitor 9, as the N-channel transistor 7 remains at its "on" state, the node B connected with the drain of the Y-selector 5 assumes a level slightly lower than the inversion level of the complementary inverter 8.
The potential at the node A change in such a manner that it follows the potential at the node B. That is, during the charging of the parasitic capacitor 9 of the digit line C, the potential at the node A becomes lower than the "V.sub.DD -threshold level of the P-channel transistor". Here, the V.sub.DD represents the potential of the power supply source. After the completion of charging of the capacitor 9, it becomes slightly lower than the "V.sub.DD -threshold level of the P-channel transistor" and thus the P-channel transistors 1 and 2 are turned on.
Generally, the potential level at a node D, that is, an output node of the sense amplifier circuit is varied according to the ratio between the transconductance of the P-channel transistor 2 (hereinafter referred to as "gmP") and the transconductance of the N-channel transistor 4 (hereinafter referred to as "gmN"). The transistors 2, 4 forming the ratio inverter are so designed that the level at the output node D takes a high level when the gmP is higher than the gmN. Thus, while the P-channel transistor 2 is in its on-state, as the gmP is larger than the gmN, a high level output is provided at the output node D.
In the case where a high level input is inputted on the input terminals A1 and A2 at an instant t2, as shown in FIG. 3, the N-channel transistor 6 in the semiconductor memory section is selected. However, the transistor 6 remains "off" at this time. This equivalently means that the N-channel transistor 6 is not provided. Thus, only the Y-selector 5 is turned on.
As also shown in FIG. 3, the potential at the node B thus momentarily becomes lower than the inversion level of the complementary inverter 8 in charging the parasitic capacitor 9 of the digit line C, and after the completion of charging of the parasitic capacitor 9 it becomes slightly higher than the inversion level of the complementary inverter 8.
The level at the node A follows that at the node B. That is, during the period of charging of the parasitic capacitor 9, the level at the node A becomes lower than the "V.sub.DD -threshold level of P-channel transistor", and there is established a relation such that the gmP is larger than the gmN because the P-channel transistors 1, 2 are in their on-states. Thus, during the charging of the parasitic capacitor 9 of the digit line C, the current sense amplifier circuit provides a high level output at the output node D.
After the charging of the parasitic capacitor 9 coupled to the digit line C, the node A assumes a level in the neighborhood of the "V.sub.DD -threshold level of P-channel transistor". Thus, the transconductance of each of the P-channel transistors 1 and 2 is reduced, so that the gmN becomes larger than the gmP. The current sense amplifier circuit thus provides a low level output at the output node D.
In the conventional current sense amplifier circuit, when the selection was made on the portion where an N-channel transistor (hereinafter referred to as "memory cell") is not formed in the semiconductor memory section, the output of the current sense amplifier circuit becomes momentarily a high level for charging the parasitic capacitor coupled to the digit line. While the capacitor coupled to the digit line is being charged, the output remains a high level, and after the completion of the charging, the current sense amplifier circuit becomes a condition wherein a normal low level is outputted. While the output of the current sense amplifier circuit stays at its high level, the output data is invalid, thus extending the access time (shown as "TAC2" in FIG. 3) in the semiconductor memory device. This is one problem to be solved in the conventional circuit.
Recently, with an increase in the memory capacity, there is an increase in the number of memory cells coupled to the digit line in the digit line direction. This means that there is a tendency to increase the charging period of the digit line, that is, the duration TAC2 in FIG. 3 increases in accordance with an increase in the memory capacity.
Further, in the conventional circuit, the gate potential of the N-channel transistor 3 is in the neighborhood of an intermediate level between the power supply potential and the ground potential. Therefore, the transconductance of the N-channel transistor 3 is low, and thus it is impossible to charge the parasitic capacitor 9 quickly by supplying a large current I1 to the digit line C. In addition, since the gate potential of the P-channel transistor 1 of the current-mirror circuit is an intermediate level between the "power supply potential-threshold level of P-channel transistor" and the ground potential, the transconductance of the P-channel transistor 1 is also low. This means that the current I1 for charging the parasitic capacitor 9 coupled to the digit line C is small, thus further extending the access time TAC2. This is another problem to be solved in the conventional circuit.